1. Field of the Invention
The present invention generally relates to a branch target buffer (BTB) of a processor of computer architecture, and more specifically to a branch target buffer system and method for storing target address, applicable to a 16-bit, 32-bit, 64-bit or higher processor architecture. When the target address of the branch instruction is stored, the BTB stores the variation range, carry bit and sub/add bit of the target address without having to store all the bits of the target address, for reducing the number of bits of the target address field for the BTB of the processor.
2. The Prior Arts
The branch target buffer (BTB) is for storing the target address of the branch instruction, and is often used to determine whether an instruction is a branch instruction. If an instruction is determined to be a branch instruction, the branch predictor will determine whether the branch instruction will be taken or not, based on the branch history of the branch instruction. If the branch predictor predicts that a branch will be taken, the target address field of the BTB will provide the target address for the program to continue.
FIG. 1 shows a schematic view of the operation of a conventional BTB for storing the target address of a branch instruction. As shown in FIG. 1, a BTB 10 stores the history of a target branch. The BTB 10 has a plurality of entries 101. The number of entries can be, for example, 512 (512-entry).
Each entry 101 of the BTB 10 includes a tag 102, and a data 103. The tag 102 is the [31:9]-bit of the branch instruction address that is previously executed, and the data 103 includes a target address ([31:0]) 104 of a previously executed branch instruction, and a 2-bit history information 105.
The BTB 10 will fetch the current instruction address and check whether the instruction address is a branch instruction previously executed. The [8:2]-bit of the current address is used to read the tag 102, and compared to the [31:9]-bit of the current instruction address. If the tag of the current branch instruction address is the same as the tag 102 in the cache, the 2-bit history information 105 in the data 103 will indicate that the branch instruction is often fetched, and the BTB 10 will use the target address 104 as the instruction address to be passed to the instruction cache. The 2-bit history information 105 of the data 103 represents four possibilities of the entry 101 of the BTB 10.
In conventional technology, when the BTB stores the target address of the branch instruction, the BTB must store all the bits of the target address. Therefore, the large number of bits of the BTB prevents the chip size and the power consumption from reduction. Therefore, it remains a problem to be solved for the development of a BTB with smaller number of bits and applicable to a 16-bit, 32-bit, 64-bit, or even higher processor architecture to generate a complete target address to achieve the computation performance as well as reduce the chip size and power consumption.